The present invention relates to semiconductor device processing, and more specifically, to utilizing fill shapes and patterns during the processing.
Multiple-step patterning processes that require pattern/etch transfer between multiple lithography steps (e.g., double etch double exposure (DE2)) typically transfer the pattern into an intermediate hardmask material. Control of the intermediate pattern transfer is critical to multiple patterning. There are, however, process sensitivities that make the intermediate etch patterning difficult to control with a timed etch. Overcoming these difficulties may require the utilization of an optical endpoint to ensure that the etching process does not remove too much material.
For example, in the instance where a gate is to be formed and then cut the following multiple step process may begin with a resist layer being patterned to overlay the gate material. In many instances, the gate material overlays a gate oxide layer. The exposed gate material is then removed with a first process to leave a gate strip in the area under the resist pattern. Then, two or more portions of the gate are again covered with a layer of resist. The exposed portions are then exposed to a timed etch. The underlying gate oxide layer may serve as the optical endpoint for the time etch. However, in the event that the gate is narrow or the width of the exposed portions is minimal, there may not be enough gate oxide to serve as an effective optical endpoint.